Why is "GDSII" trending?

Search Interest Perspective

• Low-power design and implementation of an enhanced I2C bus controller using open lane: from RTL to GDSII - Nature
• Startup Wants to Speed Up Chip Design With AI in RTL to GDSII Path - EE Times
• Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU - Adafruit
• A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL) - Semiconductor Engineering
• AI agent designs RISC-V processor in 12 hours from 219-word specification - Mezha
• Revolution in chipmaking: AI designed a RISC-V processor from scratch in a record 12 hours - hi-Tech.ua
• Matt Venn's Tiny Tapeout Gets a Shiny New Interactive Chip Viewer for Easy Project Browsing - Hackster.io
• 3D GDSII Viewer goes Open Source - Universiteit Twente
• Three Ways to Accelerate Cell Layout in DTCO - All About Circuits
• Persistent PCells Click With OpenAccess - Electronic Design
• Architect Labs nabs $24M to speed up chip design projects with AI - SiliconANGLE
• Improving yield in RTL-to-GDSII flows - EE Times
• AI agent designs a complete RISC-V CPU from a 219-word spec sheet in just 12 hours — comparably simple design required 'many tens of billions of tokens' - Tom's Hardware
• Google joins OpenROAD EDA initiative - Electronics Weekly
• An AI agent just designed a complete RISC-V CPU from scratch in 12 hours - TechSpot
• Wafer Scale Yields Millions Of Qubits - Quantum Zeitgeist
• Hardware Trojan Detection Case Study Based on 4 Different ICs Manufactured in Progressively Smaller CMOS Process Technologies - Semiconductor Engineering
• Microfluidics chips fabrication techniques comparison - Nature
• Leveraging the Advantages of OASIS Files - EE Times
• Going from GDSII to OASIS - EE Times
• efabless, Google and SkyWater Are Enabling Us Mere Mortal Makers to Design Our Own Open Source ASICs - Hackster.io
• QuickLogic and PQSecure Enable Reprogrammable Post-Quantum Cryptography for SoCs - TradingView
• Crossing The Chasm: Uniting SoC And Package Verification - Semiconductor Engineering
• GDSII-based flow speeds mask data preparation - EE Times
• GloFo certifies 20nm and 14nm design flows - Electronics Weekly
• Khosla Ventures joins US AI chip design startup’s $46m round - Tech in Asia
• BSIA, SICIP team up to build semiconductor workforce - The Financial Express
• BSIA signs contract with SICIP to train 3,500 skilled professionals - Bangladesh Sangbad Sangstha (BSS)
• MosChip Delivers a Custom SoC to ISRO’s Space Applications Centre (SAC) for India’s Satellite Navigation Program - Bisinfotech