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Single instruction, multiple threads (SIMT) is an execution model used in parallel computing where a single central "control unit" broadcasts an instruction to multiple "processing units" for them to all optionally perform simultaneous synchronous and fully-independent parallel execution of that one instruction. Each PU has its own independent data and address registers, its own independent memory, but no PU in the array has a program counter. In Flynn's 1972 taxonomy this arrangement is a variation of SIMD termed an array processor.
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